1. Field of the Invention
The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a triple operation voltage device.
2. Description of Related Art
Due to different electrical properties required for different operation voltages, semiconductor devices such as triple operation voltage devices operated in high voltage, middle voltage and low voltage are not rare in the integrated circuits. In order to increase integration of the device, it is necessary to apply a production process of a smaller size. Furthermore, anti-punch-through doping or multi-step well doping must be applied to prevent the leakage current in the triple operation voltage device.
FIG. 1A is a schematic top view of a conventional triple operation voltage device, and FIG. 1B is a schematic cross-sectional view of the conventional triple operation voltage device in FIG. 1A. As shown in FIGS. 1A and 1B, the LV device well 130 and the MV device well 140 are separately isolated by an N-type buried layer 122 and a high voltage (HV) N-type well 124 in the P-type substrate 110.
The LV device well 130 and the MV device well 140 are separated by their corresponding HV N-type well 124 for the prevention of the leakage current. However, it should be noted that the space between the LV device well 130 and the MV device well 140 is limited by the width of the HV N-type wells 124 and the P-type substrate 110 there between. For example, the width of each HV N-type well 124 may be 7 μm and the width of the P-type substrate 110 there between may be 4 μm. Thus, the space between the LV device well 130 and the MV device well 140 is about 18 μm. Therefore, the layout area of the triple operation voltage device can't further be reduced and the integration of the integrated circuits is restricted.